Zero Aliasing for Modeled Faults

When using Built-In Self Test (BIST) for testing VLSI circuits the circuit response to an input test sequence, which may consist of thousands to millions of bits, is compacted into a signature which consists of only tens of bits. Usually a linear feedback shift register (LFSR) is used for response compaction via polynomial division. The compacting function is a many-to-one function and as a result some erroneous responses may be mapped to the same signature as the good response. This is known as aliasing. In this paper we deal with the selection of a feedback polynomial for the compacting LFSR, such that an erroneous response resulting from any modeled fault is mapped to a signature that is diierent from that for the good response. Such LFSRs are called zero-aliasing LFSRs. Only zero-aliasing LFSRs with primitive or irreducible feedback polynomials are considered due to their suitability for BIST test pattern generation. Upper bounds are derived for the least degree irreducible and primitive zero-aliasing LFSR polynomials. These bounds show that in all practical test applications such a polynomial will be of degree less than 53. Expected bounds are derived and show that when the number of faults is less than 10 6 , then this degree is at most 21. Procedures to nd irreducible and primitive zero-aliasing LFSR polynomials of: (i) the smallest degree and (ii) a pre-speciied degree; are presented. A low-complexity procedure to nd a zero-aliasing LFSR polynomial has also been presented. The worst case as well as expected time complexities of all these procedures are derived. Experimental results are presented for practical problem sizes to demonstrate the applicability of the proposed procedures.